Integrated circuit memory devices are widely used for consumer, commercial and industrial applications. As is well known to those having skill in the art, integrated circuit memory devices may be divided into Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices. DRAM devices require refresh to prevent the data that is stored therein from being lost. SRAM devices, on the other hand, do not require refresh. As is well known to those having skill in the art, a DRAM memory cell may include a transistor, such as a field effect transistor, often referred to as a Metal Oxide Semiconductor (MOS) transistor, and a capacitor.
As is also well known to those having skill in the art, a DRAM device includes a cell array region and a peripheral circuit region, The cell array region has a plurality of active regions, which are two dimensionally arrayed along rows and columns, and a pair of word lines crossing over the respective active regions. Also, first and second source regions are formed at respective opposite ends of the respective active regions, and common (shared) drain regions are formed at the active regions between the pair of word lines. Therefore, a pair of access transistors are disposed in each of the respective active regions.
In addition, first and second cell capacitors are formed over the first and second source regions, respectively. The respective first and second cell capacitors are electrically connected to the respective first and second source regions. As a result, a pair of cells is formed at each of the active regions. Each of the cell capacitors comprises a lower or storage node electrically connected to the first or second source region, a dielectric layer stacked on the storage node, and an upper or plate electrode stacked on the dielectric layer.
In a conventional DRAM cell, the storage node has an oval shape or a rectangular shape when viewed from a top plan view. In other words, the storage node has a width, which is less than a length thereof. The width of the storage node is typically equal to a half of the length thereof. Thus, in the event that the height of the storage nodes is increased in order to increase the capacity of the cell capacitors, the storage nodes may lean toward a width direction thereof. In particular, when the substrate having the storage nodes is rotated to remove cleaning solution or deionized water from the substrate, the storage nodes may lean toward a width direction thereof. Accordingly, the adjacent storage nodes may electrically connect to each other, thereby generating two-bit fail.
A DRAM device having rectangular polygon-shaped storage nodes or circle-shaped storage nodes is taught in the Japanese laid-open patent number 2000-150824. The semiconductor device comprises a plurality of active regions, which are two dimensionally arrayed along rows and columns. The active regions include first through fourth active regions. The first active regions are disposed to have a first pitch and a second pitch along x-axis and y-axis, respectively. Here, the x-axis and the y-axis are parallel with the rows and the columns respectively. The second active regions are arrayed at positions relative to the first active regions that are parallel-shifted by a quarter of the first pitch and a quarter of the second pitch along the x-axis and the y-axis respectively, and the third active regions are arrayed at positions relative to the first active regions that are parallel-shifted by a half of the first pitch and a half of the second pitch along the x-axis and the y-axis, respectively. Similarly, the fourth active regions are arrayed at positions relative to the first active regions that are parallel-shifted by three quarters of the first pitch and three quarters of the second pitch alone the x-axis and the y-axis, respectively. Also, a first source region is formed at one end of the active regions and a second source region is formed at another end of the active regions. Storage nodes are formed over the first and second source regions.
According to the Japanese laid-open patent number 2000-150824, it may be difficult to increase an alignment margin during formation of the storage nodes, since a space between a bit line pad and a storage node contact hole adjacent to the bit line pad may be less than a minimum design rule. In addition, it may be desirable to increase channel widths and channel lengths of access MOS transistors in order to improve characteristics of the access MOS transistors formed at the active regions. In other words, there may be a need to increase widths of word lines that overlap with the active regions and widths of the active regions that overlap with the word lines. However, according to the layout of the active regions disclosed in the Japanese laid-open patent No. 2000-150824, it may not be easy to increase the widths of the word lines that overlap with the active regions and the widths of the active regions that overlap with the word lines.